As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues. HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure, such as a stack of alternating silicon and silicon:germanium alloy (SiGe) layers, arranged in a vertical configuration.
To form complementary metal oxide semiconductor (CMOS) devices, in many approaches the p-type FET (PFET) device is formed with a gate having a first work function metal, while the n-type FET (NFET) is formed with a gate having a second work function metal. This approach may entail formation of the first work function metal across the whole device, while the first work function metal is subsequently selectively removed from the NFET portion of a CMOS device, to be replaced with the appropriate, second work function metal on NFET gates. For nanosheet devices, operable techniques do not exist for selectively removing the first work function metal from NFET regions while not damaging PFET regions.
With respect to these and other considerations, the present disclosure is provided.